1. Field of the Invention
The present invention relates to a method for manufacturing and testing integrated circuits and, more specifically, to a method for testing integrated circuits directly on a semiconductor wafer and for preparing such integrated circuits for their encapsulation.
2. Discussion of the Related Art
Generally, integrated circuits formed on a semiconductor wafer are tested for a first time directly on the wafer. This test is carried out by means of test tips which are placed on contact pads of the integrated circuits and which enable electrically testing the circuits. Connection elements, for example, conductive bonding layers on which conductive bumps are formed, are then formed on the contact pads. After this, the integrated circuits are cut up into chips and the defective chips are eliminated. The integrated circuits are finally placed on a support and packaged. A second test is generally performed after this encapsulation step.
Integrated circuits belonging to the category of surface-mounted components (SMC) and, more specifically, of flip-chip integrated circuit chip assemblies are here considered.
During the test performed on the still uncut wafer, test tips are pressed on the contact pads formed on one surface of the integrated circuits. This pressing has the disadvantage of forming, on the contact pads, scratches which may raise problems of reliability of the connection elements formed on the contact pads. This is particularly critical when the size of integrated circuits, and thus the size assigned to the contact pads, is decreased.
To overcome this problem, it has been provided to use contact pads formed of two parts. The first part, here called the test pad, is used as a test tip pressing area and the other part, here called the connection pad, is provided for the assembly of the connection elements intended to attach the integrated circuit chip on a support. Thus, the scratches formed by the pressing of the test tips are located at the level of the test pads, these pads being no longer used hereafter. The contact between the chip and the connection elements is then ensured at the connection pad level.
However, the use of contact pads formed of two elementary pads, and thus having a relatively large surface area, is a problem when considering radio-frequency circuits, that is, circuits operating at frequencies greater than 800 MHz, or circuits having high switching frequencies.
Indeed, the test pads, which remain biased to the same voltage as the connection pads, form antennas or at least form stray capacitances and inductances with elements present in the integrated circuit next to the contact pads or in layers below said pads.
A solution for avoiding the problems of formation of parasitic components in the circuit would be to disconnect the test and the connection pads when probing is complete. Japanese patent application JP 02241046 presents this solution, the test and the connection pads being “cut” after probing. However, this cutting requires additional fabrication steps, for example a laser cut. It would be desirable to realize this disconnection without increasing the number of fabrication steps.